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7/15/99 v 3.2 datasheet page 1 preliminary copy powerpc 750 tm scm risc microprocessor advance information powerpc 750 tm scm risc microprocessor datasheet the powerpc 750 tm microprocessor is an implementation of the powerpc tm family of reduced instruction set computer (risc) microprocessors. in this document, the term 750 is used as an abbreviation for the phrase powerpc 750 tm microprocessor. this document contains pertinent physical characteristics of the 750 single chip modules (scm). this document contains the following topics. topic page overview....................................................................................................................... ............................... 2 features ....................................................................................................................... ............................... 3 general parameters ............................................................................................................. ....................... 6 electrical and thermal characteristics ......................................................................................... ............... 7 powerpc 750 microprocessor pin assignments ..................................................................................... .. 23 powerpc 750 microprocessor pinout listings ..................................................................................... ..... 24 powerpc 750 microprocessor package description................................................................................. 27 system design information ...................................................................................................... ................. 29 ordering information........................................................................................................... ....................... 41 the powerpc name, the powerpc logotype, and powerpc 750 are trademarks of international business machines corporation. this document contains information on a new product under development by ibm. ibm reserves the right to change or discontinue this product with- out notice. ? ibm corporation, 1998 portions hereof ? international business machines corporation, 1991-1998. all rights reserved.
page 2 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy overview the 750 is targeted for high performance, low power systems and supports the following power management features; doze, nap, sleep, and dynamic power management. the 750 consists of a processor core and an internal l2 tag combined with a dedicated l2 cache interface and a 60x bus. figure 8 shows a block diagram of the 750. figure 8. 750 block diagram. fxu2 gprs lsu fprs fpu instruction fetch system completion rename rename buffers buffers unit 32k icache 32k dcache bht / biu biu 60x l2 cache fxu1 l2 tags dispatch branch unit btic control unit
7/15/99 v 3.2 datasheet page 3 preliminary copy powerpc 750 tm scm risc microprocessor features this section summarizes features of the 750s implementation of the powerpc architecture. major features of the 750 are as follows. ? branch processing unit - four instructions fetched per clock. - one branch processed per cycle (plus resolving 2 speculations). - up to 1 speculative stream in execution, 1 additional speculative stream in fetch. - 512-entry branch history table (bht) for dynamic prediction. - 64-entry, 4-way set associative branch target instruction cache (btic) for eliminating branch delay slots. ? dispatch unit - full hardware detection of dependencies (resolved in the execution units). - dispatch two instructions to six independent units (system, branch, load/store, ?xed-point unit 1, ?xed-point unit 2, or ?oating-point). - serialization control (predispatch, postdispatch, execution, serialization). ? decode - register ?le access. - forwarding control. - partial instruction decode. ? load/store unit - one cycle load or store cache access (byte, half-word, word, double-word). - effective address generation. - hits under misses (one outstanding miss). - single-cycle misaligned access within double word boundary. - alignment, zero padding, sign extend for integer register ?le. - floating-point internal format conversion (alignment, normalization). - sequencing for load/store multiples and string operations. - store gathering. - cache and tlb instructions. - big- and little-endian byte addressing supported. - misaligned little-endian support in hardware.
page 4 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy ? fixed-point units - fixed-point unit 1 (fxu1); multiply, divide, shift, rotate, arithmetic, logical. - fixed-point unit 2 (fxu2); shift, rotate, arithmetic, logical. - single-cycle arithmetic, shift, rotate, logical. - multiply and divide support (multi-cycle). - early out multiply. ? floating-point unit - support for ieee-754 standard single- and double-precision ?oating-point arithmetic. - 3 cycle latency, 1 cycle throughput, single-precision multiply-add. - 3 cycle latency, 1 cycle throughput, double-precision add. - 4 cycle latency, 2 cycle throughput, double-precision multiply-add. - hardware support for divide. - hardware support for denormalized numbers. - time deterministic non-ieee mode. ? system unit - executes cr logical instructions and miscellaneous system instructions. - special register transfer instructions. ? cache structure - 32k, 32-byte line, 8-way set associative instruction cache. - 32k, 32-byte line, 8-way set associative data cache. - single-cycle cache access. - pseudo-lru replacement. - copy-back or write-through data cache (on a page per page basis). - supports all powerpc memory coherency modes. - non-blocking instruction and data cache (one outstanding miss under hits). - no snooping of instruction cache. ? memory management unit - 128 entry, 2-way set associative instruction tlb. - 128 entry, 2-way set associative data tlb. - hardware reload for tlb's.
7/15/99 v 3.2 datasheet page 5 preliminary copy powerpc 750 tm scm risc microprocessor - 4 instruction bat's and 4 data bats. - virtual memory support for up to 4 exabytes (2 52 ) virtual memory. - real memory support for up to 4 gigabytes (2 32 ) of physical memory. ? level 2 (l2) cache interface - internal l2 cache controller and 4k-entry tags; external data srams. - 256k, 512k, and 1 mbyte 2-way set associative l2 cache support. - copy-back or write-through data cache (on a page basis, or for all l2). - 64-byte(256k/512k) and 128-byte (l-mbyte) sectored line size. - supports ?ow-through (reg-buf) synchronous burst srams, pipelined (reg-reg) synchronous burst srams, and pipelined (reg-reg) late-write synchronous burst srams - design supports core-to-l2 frequency divisors of ? 1, ? 1.5, ? 2, ? 2.5, and ? 3. however, this specification supports the l2 frequency range specified in section, l2 clock ac spec- ifications on page 15. for higher l2 frequencies not supported in this document, please contact your ibm marketing representative. ? bus interface - compatible with 60x processor interface. - 32-bit address bus. - 64-bit data bus. - bus-to-core frequency multipliers of 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x,7.5x, and 8x supported. ? integrated power management - low-power 2.7/3.3-volt design. - three static power saving modes: doze, nap, and sleep. - automatic dynamic power reduction when internal functional units are idle. ? integrated thermal management assist unit - on-chip thermal sensor and control logic. - thermal management interrupt for software regulation of junction temperature. ? testability - lssd scan design. - jtag interface. ? reliability and serviceability; parity checking on 60x and l2 cache buses
page 6 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy general parameters the following list provides a summary of the general parameters of the 750. technology 0.25 m m cmos, five-layer metal die size 7.56 mm x 8.79 mm (67 mm 2 ) transistor count 6.35 million logic design fully-static packages 750: surface mount 360-lead ceramic ball grid array (cbga) with l2 interface. core power supply 2.7 50mv dc i/o power supply 3.3 v 5% v dc
7/15/99 v 3.2 datasheet page 7 preliminary copy powerpc 750 tm scm risc microprocessor electrical and thermal characteristics this section provides both ac and dc electrical specifications and thermal characteristics for the 750. dc electrical characteristics the tables in this section describe the 750s dc electrical characteristics. table 1 provides the absolute max- imum ratings. table 2 provides the recommended operating conditions for the 750. table 1. absolute maximum ratings characteristic symbol value unit core supply voltage v dd -0.3 to 2.75 v pll supply voltage av dd -0.3 to 2.75 v l2 dll supply voltage l2av dd -0.3 to 2.75 v 60x bus supply voltage ov dd -0.3 to 3.6 v l2 bus supply voltage l2ov dd -0.3 to 3.6 v input voltage v in -0.3 to 3.6 v storage temperature range t stg -55 to 150 c note: 1. functional and tested operating conditions are given in table 2. absolute maximum ratings are stress ratings only, and func- tional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause per- manent damage to the device. 2. caution: v in must not exceed ov dd by more than 0.3v at any time, including during power-on reset. 3. caution: ov dd must not exceed v dd /av dd by more than 1.2v at any time, including during power-on reset. 4. caution: v dd /av dd must not exceed ov dd by more than 0.4v at any time, including during power-on reset.
page 8 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy table 3 provides the package thermal characteristics for the 750. the 750 incorporates a thermal management assist unit (tau) composed of a thermal sensor, digital-to-ana- log converter, comparator, control logic, and dedicated special-purpose registers (sprs). see the 750 risc microprocessor users manual for more information on the use of this feature. specifications for the thermal sensor portion of the tau are found in table 4. table 5 provides dc electrical characteristics for the 750. table 2. recommended operating conditions characteristic symbol value unit core supply voltage v dd 2.65 to 2.75 v pll supply voltage av dd 2.65 to 2.75 v l2 dll supply voltage l2av dd 2.65 to 2.75 v 60x bus supply voltage ov dd 3.135 to 3.465 v l2 bus supply voltage l2ov dd 3.135 to 3.465 or v dd v input voltage v in gnd to ov dd v die-junction temperature t j 0 to 65 c note: these are recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. table 3. package thermal characteristics characteristic symbol value unit cbga package thermal resistance, junction-to-case thermal resistance (typical) q jc 0.03 c/w cbga package thermal resistance, junction-to-lead thermal resistance (typical) q jb 3.8 c/w note: refer to section, thermal management information on page 34 for more information about thermal management. table 4. thermal sensor speci?cations see table 2 for operating conditions. num characteristic min max unit notes 1 temperature range 0 128 c 1 2 comparator settling time 20 ms 2 3 resolution 4 c 3 note: 1.the temperature is the junction temperature of the die. the thermal assist unit's (tau) raw output does not indicate an absolute temperature, but it must be interpreted by software to derive the absolute junction tem- perature. for information on how to use and calibrate the tau, contact your local ibm sales of?ce. this spec- i?cation re?ects the temperature span supported by the design. 2. the comparator settling time value must be converted into the number of cpu clocks that need to be written into the thrm3 spr. 3. this value is guaranteed by design and is not tested.
7/15/99 v 3.2 datasheet page 9 preliminary copy powerpc 750 tm scm risc microprocessor table 6 provides the power consumption for the 750. table 5. dc electrical speci?cations see table 2 for operating conditions . characteristic symbol min max unit notes input high voltage (all inputs except sysclk) v ih 2.0 3.465 v 1,2 input low voltage (all inputs except sysclk) v il gnd 0.8 v sysclk input high voltage cv ih 2.4 ov dd v1 sysclk input low voltage cv il gnd 0.4 v input leakage current, v in = ov dd i in 30 m a 1,2 hi-z (off state) leakage current, v in = ov dd i tsi 30 m a 1,2 output high voltage, i oh = C6ma v oh 2.4 v output low voltage, i ol = 6ma v ol 0.4 v capacitance, v in =0v, f = 1mhz c in 5.0 pf 2,3 note: 1. for 60x bus signals, the reference is ov dd , while l2ov dd is the reference for the l2 bus signals. 2. excludes test signals lssd_mode, l1_tstclk, l2_tstclk, and ieee 1149.1 signals. 3. capacitance values are guaranteed by design and characterization, and are not tested. table 6. power consumption see table 2 for operating conditions . processor cpu frequency unit notes 200 mhz 225/233 mhz 250/266 mhz 275 mhz 300 mhz full-on mode typical maximum 4.7 5.6 6.5 6.7 7.3 w 1,3,4,5 7.5 8.8 9.8 10.1 11.0 w 1,2,4,5 doze mode maximum 1.6 1.8 2.1 2.2 2.3 w 1,2,5 nap mode maximum 250 250 250 250 250 mw 1,2,5 sleep mode maximum 100 100 100 100 100 mw 1,2,5 note: 1. these values apply for all valid 60x bus and l2 bus ratios. the values do not include i/o supply power (ov dd and l2ov dd ) or pll/dll supply power (av dd and l2av dd ). ov dd and l2ov dd power is system dependent, but is typically <10% of v dd power. worst case power consumption for av dd = 15mw and l2av dd = 15mw. 2. maximum power is measured at v dd = 2.75. 3. typical power is an average value measured at v dd = av dd = l2av dd = 2.7v, ov dd = l2ov dd = 3.3v in a system execut- ing typical applications and benchmark sequences. 4. full-on mode uses a worst case instruction mix. 5. guaranteed by design and characterization, and is not tested.
page 10 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy ac electrical characteristics this section provides the ac electrical characteristics for the 750. after fabrication, parts are sorted by maxi- mum processor core frequency as shown in section , clock ac specifications, and tested for conformance to the ac specifications for that frequency. these specifications are for 200, 225, 233, 250, 266, 275, and 300 mhz processor core frequencies. the processor core frequency is determined by the bus (sysclk) fre- quency and the settings of the pll_cfg(0-3) signals. parts are sold by maximum processor core frequency (see section, ordering information on page 41). clock ac speci?cations table 7 provides the clock ac timing specifications as defined in figure 9. table 7. clock ac timing speci?cations see table 2 for operating conditions. num characteristic 200 mhz * 225/233 mhz 250/266 mhz 275 mhz 300 mhz * unit notes min max min max min max min max min max processor frequency 150 200 150 233 150 266 150 275 200 300 mhz vco frequency 300 400 300 466 300 533 300 550 400 600 mhz sysclk frequency 25 83.3 25 83.3 25 83.3 25 83.3 25 100 mhz 1 1 sysclk cycle time 12 40 12 40 12 40 12 40 10 40 ns 2,3 sysclk rise and fall time 2.0 2.0 2.0 2.0 2.0 ns 2,3 4 sysclk duty cycle measured at 1.4 v 40 60 40 60 40 60 40 60 40 60 % 3 sysclk jitter 150 150 150 150 150 ps 4,3 internal pll relock time 100 100 100 100 100 m s 5 note: 1. note: the sysclk frequency and the pll_cfg[0-3] settings must be chosen such that the resulting sysclk (bus) fre- quency, cpu (core) frequency, and pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0-3] signal description in section , pll con?guration, for valid pll_cfg[0-3] set- tings. 2. rise and fall times for the sysclk input are measured from 0.4 to 2.4v. 3. timing is guaranteed by design and characterization, and is not tested. 4. the total input jitter (short term and long term combined) must be under 150ps. 5. relock timing is guaranteed by design and characterization, and is not tested. pll-relock time is the maximum amount of time required for pll lock after a stable v dd and sysclk are reached during the power-on reset sequence. this speci- ?cation also applies when the pll has been disabled and subsequently re-enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the power-on reset sequence. * subject to availability - see your marketing representative.
7/15/99 v 3.2 datasheet page 11 preliminary copy powerpc 750 tm scm risc microprocessor 60x bus input ac speci?cations table 8 provides the 60x bus input ac timing specifications for the 750 as defined in figure 10and figure 11. input timing specifications for the l2 bus are provided in section, l2 bus input ac specifications on page 17. figure 9. sysclk input timing diagram table 8. 60x bus input timing speci?cations 1 see table 2 for operating conditions. num characteristic 200, 225, 233, 250, 266, 275 mhz 300 mhz unit notes min max min max 10a address/data/transfer attribute inputs valid to sysclk (input setup) 2.5 2.5 ns 2 10b all other inputs valid to sysclk (input setup) 3.0 2.5 ns 3 10c mode select input setup to hreset (drtry, tlbisync) 8 8 t sysclk 4,5,6,7 11a sysclk to address/data/transfer attribute inputs invalid (input hold) 1.0 0.8 ns 2 11b sysclk to all other inputs invalid (input hold) 1.0 0.8 ns 3 11c hreset to mode select input hold ( drtry, tlbisync) 0 0 ns 4,6,7 note: 1. input speci?cations are measured from the ttl level (0.8 to 2.0v) of the signal in question to the 1.4v of the rising edge of the input sysclk. input and output timings are measured at the pin (see figure 10 ). 2. address/data transfer attribute inputs are composed of the following: a[0-31], ap[0-3], tt[0-4], tbst, tsiz[0-2], gbl, dh[0-31), dl[0-31], dp[0-7]. 3. all other signal inputs are composed of the following: ts, abb, dbb, ar tr y, bg, aa ck, dbg, dbw o, t a, dr tr y, tea, dbdis, tben, qa ck, tlbisync. 4. the setup and hold time is with respect to the rising edge of hreset (see figure 11). 5. t sysclk , is the period of the external clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in ns) of the parameter in question. 6. these values are guaranteed by design, and are not tested. 7. this speci?cation is for con?guration mode select only. also note that the hreset must be held asserted for a mini- mum of 255 bus clocks after the pll re-lock time during the power-on reset sequence. vm cv il cvih vm = midpoint voltage (1.4v) 1 4 sysclk 4 2 3
page 12 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy figure 10 provides the input timing diagram for the 750. figure 11 provides the mode select input timing diagram for the 750. figure 10. input timing diagram figure 11. mode select input timing diagram vm sysclk all inputs vm = midpoint voltage (1.4v) 10b 10a 11b 11a v ih v ih = 2.0v mode pins 10c 11c hreset
7/15/99 v 3.2 datasheet page 13 preliminary copy powerpc 750 tm scm risc microprocessor 60x bus output ac speci?cations table 9 provides the 60x bus output ac timing specifications for the 750 as defined in figure 12. output tim- ing specification for the l2 bus are provided in section l2 bus output ac specifications. table 9. 60x bus output ac timing speci?cations 1 see table 2 for operating conditions, c l = 50pf 2 num characteristic 200, 225, 233, 250, 266, 275 mhz 300 mhz unit notes min max min max 12 sysclk to output driven (output enable time) 0.5 0.5 ns 13 sysclk to output valid ( ts, abb, artry, and dbb) 6.5 6.0 ns 5 14 sysclk to all other output valid (all except ts, abb, artry, and dbb) 6.5 6.0 ns 5 15 sysclk to output invalid (output hold) 1.0 0.8 ns 3 16 sysclk to output high impedance (all signals except abb, artry, and dbb) 6.0 6.0 ns 8 17 sysclk to abb and dbb high impedance after pre- charge 1.0 1.0 t sysclk 4,6,8 18 sysclk to artry high impedance before pre- charge 5.5 5.5 ns 8 19 sysclk to artry precharge enable 0.2 x t sysclk + 1.0 0.2 x t sysclk + 1.0 ns 3,4,7 20 maximum delay to artry precharge 11 t sysclk 4,7 21 sysclk to artry high impedance after precharge 22 t sysclk 4,7,8 note: 1. all output speci?cations are measured from the 1.4v of the rising edge of sysclk to the ttl level (0.8v or 2.0v) of the signal in question. both input and output timings are measured at the pin. 2. all maximum timing speci?cations assume c l = 50pf. 3. this minimum parameter assumes cl = 0pf. 4. t sysclk is the period of the external bus clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration of the parameter in question. 5. output signal transitions from gnd to 2.0v or ov dd to 0.8v. 6. nominal precharge width for abb and dbb is 0.5 t sysclk . 7. nominal precharge width for ar tr y is 1.0 t sysclk . 8. guaranteed by design and characterization, and not tested.
page 14 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy figure 12 provides the output timing diagram for the 750. figure 12. output timing diagram sysclk all outputs (except ts, abb, dbb, artry) ts abb, dbb artry 12 14 13 15 16 16 vm vm 15 vm 13 20 18 17 21 19
7/15/99 v 3.2 datasheet page 15 preliminary copy powerpc 750 tm scm risc microprocessor l2 clock ac speci?cations table 10 provides the l2clk output ac timing specifications as defined in figure 13. table 10. l2clk output ac timing speci?cations see table 2 for operating conditions. num characteristic min max unit notes l2clk frequency 80 150 mhz 1,5, 7 22 l2clk cycle time 6.6 12.5 ns 7 23 l2clk duty cycle 50 % 2 l2clk jitter 150 ps 3,6 internal dll-relock time 640 l2clk 4 note: 1. l2clk outputs are l2clkouta, l2clkoutb, and l2sync_out pins. the internal design supports higher l2clk fre- quencies; however, the l2 i/o drivers have been designed to support a 150mhz l2 bus loaded with 4 off-the-shelf pipe- lined synchronous burst srams. running the l2 bus beyond 150mhz would require tightly coupled customized srams or a multi-chip module (mcm) implementation. the l2clk frequency to core frequency settings must be chosen such that the resulting l2clk frequency and core frequency do not exceed their respective maximum or minimum operating frequencies. l2clkouta and l2clkoutb must have equal loading. 2. the nominal duty cycle of the l2clk is 50% measured at midpoint voltage. 3. the total input jitter (short term and long term combined) must be under 150ps. 4. the dll re-lock time is speci?ed in terms of l2clks. the number in the table must be multiplied by the period of l2clk to compute the actual time duration in nanoseconds. re-lock timing is guaranteed by design and characterization, and is not tested. 5. the l2cr [l2sl] bit should be set for l2clk frequencies less than 110mhz. 6. guaranteed by design and characterization, and not tested. 7. running the l2 up to 150mhz is speci?ed only for the 300mhz core and138mhz is speci?ed only for the 275mhz core. for all core frequencies equal or below 266mhz, the maximum l2 frequency is 133mhz.
page 16 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy the l2clk_out timing diagram is shown in figure 13. figure 13. l2clk_out output timing diagram vm vm = midpoint voltage (l2ov dd /2) 22 l2clk_outa vm vm 23 vm vm = midpoint voltage (l2ov dd /2) 22 l2clk_outa vm vm 23 l2clk_outb gnd l2ovdd vm l2clk_outb vm vm vm l2sync_out vm vm vm l2sync_out vm vm l2 single-ended clock mode l2 differential clock mode
7/15/99 v 3.2 datasheet page 17 preliminary copy powerpc 750 tm scm risc microprocessor l2 bus input ac speci?cations the l2 bus input interface ac timing specifications are found in table 11. figure 14 shows the l2 bus input timing diagrams for the 750. table 11. l2 bus input interface ac timing speci?cations 1 see table 2 for operating conditions, l2ov dd = 3.3 5% v dc or v dd 4 num characteristic min max unit notes 29,30 l2sync_in rise and fall time 1.0 ns 2,3 24 data and parity input setup to l2sync_in 1.7 ns 25 l2sync_in to data and parity input hold 0.5 ns note: 1. all input speci?cations are measured from the midpoint voltage (1.4v) of the signal in question to the midpoint voltage of the rising edge of the input l2sync_in. input timings are measured at the pins (see figure 14). 2. rise and fall times for the l2sync_in input are measured from 0.4 to 2.4v. 3. guaranteed by design and characterization, and not tested. 4. for srams that can be operated at the v dd voltage, l2ov dd can also be tied to the v dd voltage. figure 14. l2 bus input timing diagrams vm vm = midpoint voltage (1.4v) l2sync_in 25 24 all inputs 29 30 vm vm
page 18 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy l2 bus output ac speci?cations table 12 provides the l2 bus output interface ac timing specifications for the 750 as defined in figure 15. table 12. l2 bus output interface ac timing speci?cations 1 see table 2 for operating conditions, l2ov dd = 3.3 5% v dc or v dd 7 , c l = 20pf 3 num characteristic l2cr[14-15] is equivalent to: unit notes 00 2 01 10 11 min max min max min max min max 26 l2sync_in to output valid for processors 266mhz and below 5.0 5.5 rsv 5 rsv 5 ns 26 l2sync_in to output valid for processor at 275mhz 4.5 5.0 rsv 5 rsv 5 ns 26 l2sync_in to output valid for processor at 300mhz 4.0 4.5 rsv 5 rsv 5 ns 27 l2sync_in to output hold 0.5 1.0 rsv 5 rsv 5 ns 4 28 l2sync_in to high imped- ance 4.0 4.5 rsv 5 rsv 5 ns 6 note: 1. all outputs are measured from the midpoint voltage of the rising edge of l2sync_in to the midpoint voltage (1.4v) of the signal in question. the output timings are measured at the pins. 2.the outputs are valid for both single-ended and differential l2clk modes. for ?ow-thru and pipelined reg-reg synchro- nous burst srams, l2cr[14-15] = 00 is recommended. for pipelined late-write synchronous burst srams, l2cr[14- 15] = 01 is recommended. 3. all maximum timing speci?cations assume cl = 20pf. 4. this measurement assumes cl= 5pf. 5. reserved for future use. 6. guaranteed by design and characterization, and not tested. 7. for srams that can be operated at the v dd voltage, l2ov dd can also be tied to the v dd voltage.
7/15/99 v 3.2 datasheet page 19 preliminary copy powerpc 750 tm scm risc microprocessor figure 15 shows the l2 bus output timing diagrams for the 750. figure 15. l2 bus output timing diagrams 27 vm vm = midpoint voltage (1.4v) l2sync_in 26 all outputs vm 28 l2data bus vm vm
page 20 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy ieee 1149.1 ac timing speci?cations table 13provides the ieee 1149.1 (jtag) ac timing specifications as defined in figure 16, figure 17, figure 18, and figure 19. the five jtag signals are; tdi, tdo, tms, tck, and trst. figure 16 provides the jtag clock input timing diagram. table 13. jtag ac timing speci?cations (independent of sysclk) see table 2 for operating conditions, c l = 50pf num characteristic min max unit notes tck frequency of operation 0 33.3 mhz 1 tck cycle time 30 ns 2 tck clock pulse width measured at 1.4v 15 ns 3 tck rise and fall times 0 2 ns 4 4 spec obsolete, intentionally omitted 5 trst assert time 25 ns 1 6 boundary-scan input data setup time 4 ns 2 7 boundary-scan input data hold time 15 ns 2 8 tck to output data valid 4 20 ns 3,5 9 tck to output high impedance 3 19 ns 3,4 10 tms, tdi data setup time 0 ns 11 tms, tdi data hold time 12 ns 12 tck to tdo data valid 2.5 12 ns 5 13 tck to tdo high impedance 3 9 ns 4 note: 1. trst is an asynchronous level sensitive signal. guaranteed by design. 2. non-jtag signal input timing with respect to tck. 3. non-jtag signal output timing with respect to tck. 4. guaranteed by characterization and not tested. 5. minimum spec guaranteed by characterization and not tested. figure 16. jtag clock input timing diagram tck vm vm 1 2 2 3 3 vm vm = midpoint voltage (1.4v)
7/15/99 v 3.2 datasheet page 21 preliminary copy powerpc 750 tm scm risc microprocessor figure 17 provides the trst timing diagram. figure 18 provides the boundary-scan timing diagram. figure 17. trst timing diagram figure 18. . boundary-scan timing diagram 5 trst 9 6 7 8 9 tck data inputs data outputs data outputs input data valid output data valid
page 22 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy figure 19 provides the test access port timing diagram. figure 19. test access port timing diagram 9 13 12 10 11 tck tdi, tms tdo tdo input data valid output data valid
7/15/99 v 3.2 datasheet page 23 preliminary copy powerpc 750 tm scm risc microprocessor powerpc 750 microprocessor pin assignments the following sections contain the pinout diagram for the 750 scm. ibm offers a 360 pin ceramic ball grid array package for the 750. figure 20 (in part a) shows the pinout of the 360 cbga package as viewed from the top surface. part b shows the side profile of the 360 cbga package to indicate the direction of the top surface view. figure 20. pinout of the 360 cbga package as viewed from the top surface. a b c d e f g h j k l m n p r t 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 not to scale substrate assembly. encapsulation view part b die part a 17 18 19 u v w
page 24 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy powerpc 750 microprocessor pinout listings table 14 provides the pinout listing for the 360 cbga package (the 750). table 14. pinout listing for the 360 cbga package signal name pin number active i/o a0-a31 a13, d2, h11, c1, b13, f2, c13, e5, d13, g7, f12, g3, g6, h2, e2, l3, g5, l4, g4, j4, h7, e1, g2, f3, j7, m3, h3, j2, j6, k3, k2, l2 high i/o aack n3 low input abb l7 low i/o ap0-ap3 c4, c5, c6, c7 high i/o artry l6 low i/o avdd a8 bg h1 low input br e7 low output ckstp_out d7 low output ci c2 low output ckstp_in b8 low input clkout e3 -- output dbb k5 low i/o dbdis g1 low input dbg k1 low input dbwo d1 low input dh0-dh31 w12, w11, v11, t9, w10, u9, u10, m11, m9, p8, w7, p9, w9, r10, w6, v7, v6, u8, v9, t7, u7, r7, u6, w5, u5, w4, p7, v5, v4, w3, u4, r5 high i/o dl0-dl31 m6, p3, n4, n5, r3, m7, t2, n6, u2, n7, p11, v13, u12, p12, t13, w13, u13, v10, w8, t11, u11, v12, v8, t1, p1, v1, u1, n1, r2, v3, u3, w2 high i/o dp0-dp7 l1, p2, m2, v2, m1, n2, t3, r1 high i/o drtry h6 low input gbl b1 low i/o note: 1. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 2. ov dd inputs supply power to the i/o drivers and v dd inputs supply power to the processor core. 3. internally tied to l2ov dd in the pid-8t 750 360 cbga package. this is not a supply pin. 4. these pins are reserved for potential future use as additional l2 address pins.
7/15/99 v 3.2 datasheet page 25 preliminary copy powerpc 750 tm scm risc microprocessor gnd d10, d14, d16, d4, d6, e12, e8, f4, f6, f10, f14, f16, g9, g11, h5, h8, h10, h12, h15, j9, j11, k4, k6, k8, k10, k12, k14, k16, l9, l11, m5, m8, m10, m12, m15, n9, n11, p4, p6, p10, p14, p16, r8, r12, t4, t6, t10, t14, t16 hreset b6 low input int c11 low input l1_tstclk 1 f8 high input l2addr[0-16] l17, l18, l19, m19, k18, k17, k15, j19, j18, j17, j16, h18, h17, j14, j13, h19, g18 high output l2avdd l13 l2ce p17 low output l2clkouta n15 output l2clkoutb l16 output l2data[0-63] u14, r13, w14, w15, v15, u15, w16, v16, w17, v17, u17, w18, v18, u18, v19, u19, t18, t17, r19, r18, r17, r15, p19, p18, p13, n14, n13, n19, n17, m17, m13, m18, h13, g19, g16, g15, g14, g13, f19, f18, f13, e19, e18, e17, e15, d19, d18, d17, c18, c17, b19, b18, b17, a18, a17, a16, b16, c16, a14, a15, c15, b14, c14, e13 high i/o l2dp[0-7] v14, u16, t19, n18, h14, f17, c19, b15 high i/o l2ovdd d15, e14, e16, h16, j15, l15, m16, p15, r14, r16, t15, f15 l2sync_in l14 input l2sync_out m14 output l2_tstclk 1 f7 high input l2we n16 low output l2zz g17 high output lssd_mode 1 f9 low input mcp b11 low input nc (no-connect) b3, b4, b5, a19, w19, w1, k9, k11 4 , k19 4 ovdd 2 d5, d8, d12, e4, e6, e9, e11, f5, h4, j5, l5, m4, p5, r4, r6, r9, r11, t5, t8, t12 pll_cfg[0-3] a4, a5, a6, a7 high input qack b2 low input table 14. pinout listing for the 360 cbga package signal name pin number active i/o note: 1. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 2. ov dd inputs supply power to the i/o drivers and v dd inputs supply power to the processor core. 3. internally tied to l2ov dd in the pid-8t 750 360 cbga package. this is not a supply pin. 4. these pins are reserved for potential future use as additional l2 address pins.
page 26 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy qreq j3 low output rsrv d3 low output smi a12 low input sreset e10 low input sysclk h9 input ta f1 low input tben a2 high input tbst a11 low i/o tck b10 high input tdi b7 high input tdo d9 high output tea j1 low input tlbisync a3 low input tms c8 high input trst a10 low input ts k7 low i/o tsiz0-tsiz2 a9, b9, c9 high output tt0-tt4 c10, d11, b12, c12, f11 high i/o wt c3 low output vdd 2 g8, g10, g12, j8, j10, j12, l8, l10, l12, n8, n10, n12 voltdet 3 k13 high output table 14. pinout listing for the 360 cbga package signal name pin number active i/o note: 1. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 2. ov dd inputs supply power to the i/o drivers and v dd inputs supply power to the processor core. 3. internally tied to l2ov dd in the pid-8t 750 360 cbga package. this is not a supply pin. 4. these pins are reserved for potential future use as additional l2 address pins.
7/15/99 v 3.2 datasheet page 27 preliminary copy powerpc 750 tm scm risc microprocessor powerpc 750 microprocessor package description the following sections provide the package parameters and the mechanical dimensions for the 750. parameters for the 360 cbga package the package parameters are as provided in the following list. the package type is 25x 25 mm, 360-lead ceramic ball grid array (cbga). package outline 25 x 25 mm interconnects 360 (19 x 19 ball array - 1) pitch 1.27 mm (50 mil) minimum module height 2.65 mm maximum module height 3.20 mm ball diameter 0.89 mm (35 mil) mechanical dimensions of the 360 cbga package figure 21 provides the mechanical dimensions and bottom surface nomenclature of the 360 cbga package.
page 28 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy figure 21. mechanical dimensions and bottom surface nomenclature of the 360 cbga package. notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. top side a1 corner index is a metalized feature with various shapes. bottom side a1 corner is designated with a ball missing from the array. dim min max millimeters a 2.65 3.20 a1 0.80 1.00 a2 1.10 1.30 b 0.82 0.93 d 25.00 bsc d1 5.00 16.00 e 1.27 bsc e 25.00 bsc e1 5.00 16.00 0.2 d 2x a01 corner e e1 d1 0.2 2x b a locator e 12345678910111213141516171819 u v w a b c d e f g h j k l m n p r t b c 360x a 0.3 c 0.15 b a a1 a2 c 0.15 c not to scale (18x) (18x)
7/15/99 v 3.2 datasheet page 29 preliminary copy powerpc 750 tm scm risc microprocessor system design information this section provides electrical and thermal design recommendations for successful application of the 750. pll con?guration the 750 pll is configured by the pll_cfg[0-3-] signals. for a given sysclk (bus) frequency, the pll con- figuration signals set the internal cpu and vco frequency of operation. the pll configuration for the 750 is shown in table 15 for nominal frequencies. table 15. 750 microprocessor pll con?guration pll_cfg (0:3) processor to bus fre- quency ratio (r) vco divider (d) frequency range supported by vco having an example range of vco min =300 to vco max =600 (mhz) sysclk core bin dec min= vco min /(r*d) max= vco max /(r*d) min= vco min /d max= vco max /d 0000 0 rsv 1 n/a n/a n/a n/a n/a 0001 1 7.5x 2 25 2 40 150 6 300 0010 2 7x 2 25 2 42 0011 3 pll bypass 3 n/a n/a n/a n/a n/a 0100 4 rsv 1 n/a n/a n/a 150 6 300 0101 5 6.5x 2 25 2 46 0110 6 rsv 1 n/a n/a n/a n/a n/a 0111 7 4.5x 2 33 66 150 64 300 1000 8 3x 2 50 100 5 1001 9 5.5x 2 27 54 1010 10 4x 2 37 75 1011 11 5x 2 30 60 1100 12 8x 2 25 2 38 1101 13 6x 2 25 50 1110 14 3.5x 2 43 86 5 1111 15 off 4 n/a n/a n/a off off note: 1. reserved settings. 2. sysclk min is limited by the lowest frequency that manufacturing will support, see section , clock ac speci?cations, for valid sysclk and vco frequencies. 3. in pll-bypass mode, the sysclk input signal clocks the internal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is intended for factory use only. note: the ac timing speci?cations given in the document do not apply in pll-bypass mode. 4. in clock - off mode, no clocking occurs inside the 750 regardless of the sysclk input. 5. sysclk max is valid for 300mhz core only, for slower cores, this limit is 83.3mhz as speci?ed in section, clock ac speci?cations on page 10. 6. processor frequency min is 150mhz for all core speeds including 275mhz. the frequency min is 200mhz for the 300 mhz core speed. see section , clock ac speci?cations, for valid sysclk and vco frequencies.
page 30 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy table 16 provides sample core-to-l2 frequencies. pll power supply filtering the av dd and l2av dd power signals are provided on the 750 to provide power to the clock generation phase-locked loop and l2 cache delay-locked loop respectively. to ensure stability of the internal clock, the power supplied to the av dd input signal should be filtered using a circuit similar to the one shown in figure 22. the circuit should be placed as close as possible to the av dd pin to ensure it filters out as much noise as possible. an identical but separate circuit should be placed as close as possible to the l2av dd pin. table 16. sample core-to-l2 frequencies 1 core frequency (mhz) ? 1 ? 1.5 ? 2 ? 2.5 ? 3 200 133.3 100 80 225 112.5 90 233 116.5 93.2 250 125 100 83.3 266 133 106.4 88.6 275 110 91.7 300 120 100 note: 1. although the 750 is designed for l2 bus ratios of 1:1, 1.5:1, 2:1, 2.5:1, and 3:1, this speci?cation supports the l2 fre- quency range speci?ed in section, l2 clock ac speci?cations on page 15. for higher l2 frequencies not supported in this document, please contact your ibm marketing representative. figure 22. pll power supply filter circuit vdd avdd (or l2av dd ) 10 ohm 10 mf 0.1 mf gnd
7/15/99 v 3.2 datasheet page 31 preliminary copy powerpc 750 tm scm risc microprocessor decoupling recommendations due to the 750s dynamic power management feature, large address and data buses, and high operating fre- quencies, the 750 can generate transient power surges and high frequency noise in its power supply, espe- cially while driving large capacitive loads. this noise must be prevented from reaching other components in the 750 system, and the 750 itself requires a clean, tightly regulated source of power. therefore, it is strongly recommended that the system designer place at least one decoupling capacitor with a low esr (effective series resistance) rating as close as possible to each v dd and ov dd pin (and l2ov dd for the 360 cbga) of the 750. these capacitors should range in value from 220pf to 10 m f to provide both high and low frequency filtering. suggested values for the v dd pins: 220pf (ceramic), 0.01 m f (ceramic), and 0.1 m f (ceramic). suggested val- ues for the ov dd pins: 0.01 m f (ceramic), 0.1 m f (ceramic), and 10 m f (tantalum). only smt (surface-mount technology) capacitors should be used to minimize lead inductance. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feed- ing the v dd and ov dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capaci- tors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors: 100 m f (avx tps tantalum) or 330 m f (avx tps tantalum). connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to v dd . unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external v dd , ov dd , and gnd, pins of the 750. external clock routing should ensure that the rising-edge of the l2 clock is coincident at the clk input of all srams and at the l2sync_in input of the 750. the l2clkouta network could be used only, or the l2clkoutb network could also be used depending on the loading, frequency, and number of srams. output buffer dc impedance the 750 60x and l2 i/o drivers were characterized over process, voltage, and temperature. to measure z 0 , an external resistor is connected to the chip pad, either to ov dd or gnd. then, the value of such resistor is varied until the pad voltage is ov dd /2; see figure 23. the output impedance is actually the average of two components, the resistances of the pull-up and pull- down devices. when data is held low, sw1 is closed (sw2 is open), and r n is trimmed until pad = ov dd /2. r n then becomes the resistance of the pull-down devices. when data is held high, sw2 is closed (sw1 is open), and r p is trimmed until pad = ov dd /2. r p then becomes the resistance of the pull-up devices. with a properly designed driver r p and r n are close to each other in value. then z 0 = (r p + r n )/2.
page 32 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy table 17 summarizes the impedance a board designer would design to for a typical process. these values were derived by simulation at 65c. as the process improves, the output impedance will be lower by several ohms than this typical value. figure 23. driver impedance measurement table 17. impedance characteristics v dd = 2.6 v dc , l2ov dd =ov dd = 3.3 v dc , t j = 65 c process 60x l2 symbol unit typical 43 38 z 0 w data ovdd rn sw2 sw1 pad rp gnd
7/15/99 v 3.2 datasheet page 33 preliminary copy powerpc 750 tm scm risc microprocessor pull-up resistor requirements the 750 requires high resistive (weak: 10k w ) pull-up resistors on several control signals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the 750 or other bus masters. these signals are: ts, abb, dbb, and artry. in addition, the 750 has one open-drain style output that requires a pull-up resistor (weak or stronger: 4.7k w - 1k w ) if it is used by the system. this signal is ckstp_out. during inactive periods on the bus, the address and transfer attributes on the bus are not driven by any mas- ter and may float in the high-impedance state for relatively long periods of time. since the 750 must continu- ally monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the 750 or by other receivers in the system. it is recommended that these signals be pulled up through weak (10k w ) pull-up resistors or restored in some manner by the system, the snooped address and transfer attribute inputs are: a[0-31], ap[0-3], tt[0-4], tbst, and gbl. the data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus. other data bus receivers in the system, however, may require pull-ups, or that those signals be otherwise driven by the system during inactive periods. the data bus signals are: dh[0- 31], dl[0-31], and dp[0-7]. if address or data parity is not used by the system, and the respective parity checking is disabled through hid0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left unconnected by the system. if all parity generation is disabled through hid0, than all parity checking should also be disabled through hid0, and all parity pins may be left unconnected by the system. no pull-up resistors are normally required for the l2 interface.
page 34 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy thermal management information this section provides thermal management information for the cbga package for air cooled applications. proper thermal control design is primarily dependent upon the system-level design; that is, the heat sink, air flow, and the thermal interface material. to reduce the die junction temperature, heat sinks may be attached to the package by several methods; adhesive, spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly; see figure 24. this spring force should not exceed 5.5 pounds. figure 24. package exploded cross-sectional view with several heat sink options cbga package heat sink heat sink clip adhesive or thermal interface material printed option circuit board
7/15/99 v 3.2 datasheet page 35 preliminary copy powerpc 750 tm scm risc microprocessor the board designer can choose between several types of heat sinks to place on the 750. there are several commercially-available heat sinks for the 750 provided by the following vendors. chip coolers, inc. 333 strawberry field rd. 800-227-0254 (usa/canada) warwick, ri 02887-6979 401-739-7600 thermalloy 2021 w. valley view lane p.o. box 810839 dallas, tx 75731 214-243-4321 international electronic research corporation (ierc) 135 w. magnolia blvd. burbank, ca 91502 818-842-7277 aavid engineering one kool path laconic, nh 03247-0440 603-528-3400 wakefield engineering 60 audubon rd. wakefield, ma 01880 617-245-5900 ultimately, the final selection of an appropriate heat sink for the 750 depends on many factors, such as ther- mal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. internal package conduction resistance for the exposed die packaging technology (shown in table 3), the intrinsic conduction thermal resistance paths are as follows. ? die junction-to-case thermal resistance. ? die junction-to-lead thermal resistance. figure 25 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
page 36 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy heat generated on the active side (ball) of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced- air convection. since the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may be neglected. thus, the heat sink attach material and the heat sink conduction/con- vective thermal resistances are the dominant terms. adhesives and thermal interface materials a thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. for those applications where the heat sink is attached by a spring clip mechanism, figure 26 shows the thermal performance of three thin-sheet thermal-interface materials (silicon, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. the use of ther- mal grease significantly reduces the interface thermal resistance. that is, the bare joint results in a thermal resistance approximately 7 times greater than the thermal grease joint. heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see figure 24). this spring force should not exceed 5.5 pounds. therefore the synthetic grease offers the best thermal performance, considering the low interface pressure. of course, the selection of any thermal inter- face material depends on many factors; thermal performance requirements, manufacturability, service tem- perature, dielectric properties, cost, etc. figure 25. c4 package with heat sink mounted to a printed-circuit board external resistance external resistance internal resistance (note the internal versus external package resistance) radiation convection radiation convection heat sink die/package printed-circuit board thermal interface material package/leads chip junction
7/15/99 v 3.2 datasheet page 37 preliminary copy powerpc 750 tm scm risc microprocessor figure 26. thermal performance of select thermal interface material speci?c thermal resistance (kin2/w) 0 0.5 1 1.5 2 0 10 20 30 40 50 60 70 80 contact pressure (psi) + + + silicone sheet (0.006 inch) bare joint floroether oil sheet (0.007 inch) graphite/oil sheet (0.005 inch) synthetic grease +
page 38 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy the board designer can choose between several types of thermal interfaces. heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. there are several commercially-available thermal interfaces and adhesive materials provided by the following vendors. dow-corning corporation 517-496-4000 dow-corning electronic materials p.o. box 0997 midland, mi 48686-0997 chomerics, inc. 617-935-4850 77 dragon court woburn, ma 01888-4850 thermagon, inc. 216-741-7659 3256 west 25th street cleveland, oh 44109-1668 loctite corporation 860-571-5100 1001 trout brook crossing rocky hill, ct 06067 ai technology (e.g. eg7655) 609-882-2332 1425 lower ferry road trent, nj 08618 the following section provides a heat sink selection example using one of the commercially available heat sinks.
7/15/99 v 3.2 datasheet page 39 preliminary copy powerpc 750 tm scm risc microprocessor heat sink selection example for preliminary heat sink sizing, the die-junction temperature can be expressed as follows t j = t a + t r + ( q jc + q int + q sa ) * p d where: t jj is the die-junction temperature t a is the inlet cabinet ambient temperature t r is the air temperature rise within the system cabinet q jc is the junction-to-case thermal resistance q int is the thermal resistance of the thermal interface material q sa is the heat sink-to-ambient thermal resistance p d is the power dissipated by the device typical die-junction temperatures (t j ) should be maintained less than the value specified in table 3. the temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the computer cabinet. an electronic cabinet inlet-air temperature (t a ) may range from 30 to 40 c. the air temperature rise within a cabinet (t r ) may be in the range of 5 to 10 c. the thermal resistance of the interface material ( q int ) is typically about 1 c/w. assuming a t a of 30 c, a t r of 5 c, a cbga package q jc = 0.03, and a power dissipation (p d ) of 5.0 watts, the following expression for t j is obtained: die-junction temperature: t j = 30 c + 5 c + (0.03 c/w +1.0 c/w + q sa ) * 5 w for a thermalloy heat sink #2328b, the heat sink-to-ambient thermal resistance ( q sa ) versus air flow velocity is shown in figure 27.
page 40 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy assuming an air velocity of 0.5m/s, we have an effective q sa of 7 c/w, thus t j = 30 c + 5 c + (2.2 c /w +1.0 c /w + 7 c /w) * 4.5w, resulting in a junction temperature of approximately 81 c which is well within the maximum operating temper- ature of the component. other heat sinks offered by chip coolers, ierc, thermalloy, aavid, and wakefield engineering offer different heat sink-to-ambient thermal resistances, and may or may not need air flow. though the junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of- merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. the final chip-junction operating tempera- ture is not only a function of the component-level thermal resistance, but the system-level design and its oper- ating conditions. in addition to the component's power dissipation, a number of factors affect the final operating die-junction temperature. these factors might include air flow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, next-level interconnect technology, system air temperature rise, etc. figure 27. thermalloy #2328b pin-fin heat sink-to-ambient thermal resistance versus air ?ow velocity approach air velocity (m/s) heat sink thermal resistance ( c/w) 1 2 3 4 5 6 7 8 0 0.5 1 1.5 2 2.5 3 3.5 thermalloy #2328b pin-?n heat sink (25 x 28 x 15 mm)
7/15/99 v 3.2 datasheet page 41 preliminary copy powerpc 750 tm scm risc microprocessor ordering information this section provides the part numbering nomenclature for the 750. note that the individual part numbers cor- respond to a maximum processor core frequency. for available frequencies, contact your local ibm sales office. in addition to the processor frequency and bus ratio, the part numbering scheme also consists of a part mod- ifier. the part modifier allows for the availability of future enhanced parts (that is, lower voltage, lower power, higher performance, etc.). each part number also contains a revision code. this refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. figure 28 provides the ibm part numbering nomenclature for the 750. figure 28. ibm part number key . 740 or 750 family ibm25ppc7xx--xb0xxxx0 revision level: d = (dd2.1) processor frequency no l2 data sram blank digits applic. conditions: m = 2.65v - 2.75v, 0 - 65c e = (dd2.2) package (bga) g =(dd3.0)
page 42 v 3.2 datasheet 7/15/99 powerpc 750 tm scm risc microprocessor preliminary copy ? international business machines corporation 1998 printed in the united states of america 7/99 all rights reserved this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility of liability for any use of the information contained herein. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not intended for use in implantation or other direct life support applications where mal- function may result in direct physical harm or injury to persons. no warranties of any kind, including but not limited to the implied warranties of mechantability or fitness for a particular pur- pose, are offered in this document. while the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. the information contained in this document is provided on an as is basis. in no event will ibm be liable for any damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6531 the ibm home page can be found at http://www.ibm.com the ibm microelectronics division home page can be found at http://www.chips.ibm.com the latest copy of this document can be found on the ibm website: http://www.chips.ibm.com/products/ppc ibm is a registered trademark of international business machines corporation aix, powerpc, powerpc740 and powerpc750 are trademarks of international business machines corporation.

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